In recent years, applications of wireless communications become popular quickly. For example, cell phones, wireless networks, and satellite phones have been widely used by people in their lives. Therefore, the needs of communications significantly increase, and the competition in international markets is intense. To provide a technology standard for the manufacturers to design their products, the Institute of Electrical and Electronics Engineers (IEEE) issues the IEEE 802.11 specification in 1997, which defines the physical layer (PHY layer) and media access control layer (MAC layer), and also defines the radio frequency (RF) band of 2.4 GHz, in which the data transfer rate is up to 2 Mbps. Then, the 802.11a specification focuses on industry, science and medicine (ISM) band of 5 GHz (5.15-5.35 GHz, 5.725-5.8252 GHz), in which the data transfer rate reaches 20-54 Mbps, and the 802.11b specification continues the existed 2.4 GHz physical layer.
In the development of the main chip in communication devices, there are several important factors, such as to reduce size and cost, to limit power consumption, and to improve chip performance. In the past, the transmission frequency is restricted by the low electron drift mobility of silicon elements, so the RF front-end circuits are usually implemented by GaAs transistors. In resent years, however, many new processes are developed so that the size of complementary metal-oxide-semiconductor (CMOS) elements is dramatically reduced, and the operating frequency of CMOS circuits is thereby increased. Now, CMOS processes have had the advantages of low power, high integration, and low cost, and so take an important role in the competition between integrated circuit (IC) design houses.
FIG. 1 is a block diagram of a RF receiver system 100, in which the RF signal received by an antenna 102 is amplified by a low noise amplifier 104, and mixed with an oscillating signal from a local oscillator 110 by two quadrature mixers 106 and 108, so as to be demodulated to be two signals with a desired band. The demodulated signals are further amplified by two amplifiers 112 and 114, filtered by two filters 116 and 118, and converted into two analog signals by two analog-to-digital converters (ADCs) 120 and 122 respectively. In this system 100, the low noise amplifier 104 is the dominant stage regarding the noise performance of the whole system 100. In consideration of noise figure and linearity, the low noise amplifier 104 is the most critical element of the RF receiver system 100.
Low noise amplifiers have two types, common gate configuration and cascode configuration. FIG. 2 shows a conventional cascode low noise amplifier 200, which comprises a pair of cascode transistors 202 and 204. The output transistor 202 has a drain D coupled with a load inductor L1, and a gate coupled with a bias voltage Vb. The input transistor 204 has a gate coupled with an input inductor L2, and a source S coupled with a degeneration inductor L3. The input signal of the cascode low noise amplifier 200 is Vin, and the output signal Vout is derived from the drain D of the transistor 202. For integrating all the elements of the low noise amplifier 200 into a single chip, on-chip spiral inductor is employed for the inductors L1, L2 and L3. However, the on-chip spiral inductor requires greater chip area, and its quality factor Q is restricted, so being unrealistic in applications. Further, the process of manufacturing the on-chip spiral inductor is complicated, requires higher cost, and is difficult to control the inductance of the on-chip spiral inductor. There also have been proposed to use micro electro-mechanical system (MEMS) process and other materials to improve the on-chip spiral inductor, but the effect on reducing the chip area is not significant, and the cost still cannot be reduced because the number of photomasks is increased and the elements become fragile. For cost saving, it is necessary for circuit design which requires less chip area.
An active inductor is a circuit composed of active elements for behaving as an inductor. For example, U.S. Pat. No. 6,784,749 to Cove et al uses an active inductor in the output of a limiting amplifier to improve the bandwidth and to reduce the size of the circuit. One advantage of an active inductor is that its size can be smaller than a passive inductor, so it can be used to replace an on-chip spiral inductor to reduce the circuit size. Another advantage of an active inductor is that it is adjustable, so the programmability can be expected, for example, if an active inductor is used in a low noise amplifier, the center frequency of the amplifier may be able to be programmed. However, there are still some disadvantages when using active inductor, and the worst case is that it brings greater noise, so it can be only used in low-frequency circuits, but not appropriate to high-frequency circuits. U.S. Pat. No. 6,028,496 to Ko et al. discloses a RF active inductor having high Q value, which is implemented by Si or GaAs field effect transistor (FET), and U.S. Pat. No. 7,068,130 to Redoute et al. further improves this RF active inductor to be without any independent DC voltage source to provide bias voltage.
The RF communication system market continues growing, which makes people have great interest in implementing RF elements by CMOS technology. To apply a CMOS active inductor to a RF circuit is a conception with high potential for development. A RF circuit using active inductor can reduce the chip size, and has both advantages of low cost and good circuit adaptation; for example, it can control the gain by using a current source, and improve the chip performance by adapting to the operating temperature. More importantly, a RF circuit using active inductor can control the inductance to obtain expected performance, and even can obtain high Q value easily. In Carreto-Castro et al., “RF Low-Noise Amplifiers in BiCMOS Technologies”, IEEE Trans. on Circuits and Systems, pp. 974-977, vol. 46, Issue: 7, Jul. 1999, BiCMOS is proposed to implement a RF low noise amplifier using active inductor, and is expected to reduce the noise figure (NF). However, the effect is not significant according to their experiment data. This amplifier can be only used at 1 GHz, and its NF can only reach 3.4 dB. Furthermore, the cost of BiCMOS process is very high, it is doubtful that using BiCMOS active inductor could save cost, and the performance could be good enough. In Zhuo et al., “Programmable Low Noise Amplifier with Active-Inductor Load”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, vol. 4, pp. 365-368, 1998, a common gate CMOS low noise amplifier is proposed, which uses an active inductor to replace the original on-chip spiral inductor load, and so has a good adjustable range for 1 GHz center frequency. However, replacing the load inductor which is coupled to the output of the low noise amplifier by an active inductor causes greater noise, so it also can be only used in low frequency circuits.